Achieving higher computer processing speeds has long been an object of manufacturers and users alike. In order to further the goal of high-speed processing, some computer processors employ a technique known as pipelined processing. Processors incorporating a pipelined architecture allow multiple instructions to exist in various stages of execution simultaneously.
In a pipelined architecture, a single instruction cycle may include five stages. These stages may be described sequentially as follows: (1) fetch; (2) decode; (3) access the register file; (4) execute; and (5) write to the register file. In pipelined processing, processing in each of these stages is effected in parallel to achieve high speed processing. Pipelining may be used to increase the processor speed by increasing the number of instructions completed over a period of time.
In such processors, it is possible for five instructions to co-exist in the pipeline in various stages of processing at a single time. For example, in the first several clock cycles of processing, instructions one through five may be in various stages of execution simultaneously. Completion of five-stage processing for a single instruction need not be completed before processing of a subsequent instruction may start.
For example, at one point, it is possible that instruction five is being fetched, instruction four is decoding, instruction three is accessing the register file, instruction two is executing and instruction one is being written to the register file. In pipelined processing, each instruction is generally fetched sequentially and processed sequentially in subsequent stages.
A pipelined processor must also control interrupts. Such interrupts may occur when an interrupt request signal is issued from a peripheral device or in the execution of a computer program, among other occasions. When the interrupt request occurs, the program being executed is interrupted. The processor then temporarily saves the state of the program being executed, and other processing occurs in response to the interrupt request. Once the interrupt processing is complete, the processor resumes execution of the program from the point where the program was interrupted.
Thus, a key element of the interrupted program state that must be saved is the instruction address at which program execution should resume once the interrupt processing is complete. This address is referred to as the “return address”. In some architectures, it is a requirement that this return address be saved in a particular register that is part of the general purpose register file. A problem to be solved is how to provide the interrupt mechanism with access to the register file, in order to save the return address.
Some have attempted to save the return address by using dedicated ports to the register file. However, management of the processor's register file is typically a very complex and performance-critical aspect of the design, particularly in high-frequency, deeply-pipelined, superscalar processors. An additional register file port can be costly in terms of timing, area, and power, thus reducing the effectiveness of the processor. Furthermore, many high-performance designs perform out-of-order instruction processing which can demand even more complex register file management, including register-renaming, reservation stations, and completion buffers for instruction ordering. All of these complexities make it difficult to simply provide an extra port to the register file, or even to provide special control paths to share an existing register file port, for saving the interrupt return address.